cache.h

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/*
        Copyright (C) 1997 CFU Corporation

        File: cache.h
        Description: class Cache
        Author: Chao-yinig Fu
        Date: Apr. 6 2000

        ^..^
        (00)

         $__$
        <~00~>
         (oo)
          ||

        ```````
        C ^|^ D
         \ O /
*/

#ifndef INCLUDED_CACHE_H
#define INCLUDED_CACHE_H

#include <stdio.h>
#include <math.h>

class Cache
{
public:
        Cache():_tag_array(NULL),_time_array(NULL),_valid_array(NULL),_dirty_array(NULL),_tag_array_in_stream_buffer(NULL),_valid_array_in_stream_buffer(NULL),_miss_or_hit_array(NULL) {}

        ~Cache() 
        {
                delete[] _tag_array;
                delete[] _time_array;
                delete[] _miss_or_hit_array;
                delete[] _valid_array;
                delete[] _dirty_array;

                delete[] _tag_array_in_stream_buffer;
                delete[] _valid_array_in_stream_buffer;
        }

        Cache(int c, int b, int s,int p,int wp,int use):_c(c),_b(b),_s(s),_p(p),_wp(wp),_use_stream_buffer(use),_reads(0),_writes(0),_reads_in_miss(0),_writes_in_miss(0),_writebacks(0),_sb_reads_in_miss(0),_sb_writes_in_miss(0) 
        {
                if(_c<_b || _c-_b<s)
                {
                        fprintf(stderr,"ERROR (c b s)=(%d %d %d)\n",_c,_b,_s);
                        exit(0);
                }

                _bytes_in_cache=1<<c;
                _sets_in_cache=1<<(c-b-s);
                _blocks_in_set=1<<s;
                _bytes_in_block=1<<b;

                int num_of_tags=1<<(c-b);
                _tag_array=new unsigned int[num_of_tags];
                _time_array=new unsigned int[num_of_tags];
                _miss_or_hit_array=new int[num_of_tags];
                _valid_array=new char[num_of_tags];
                _dirty_array=new char[num_of_tags];

                for(int i=0;i<_sets_in_cache;i++)
                {
                        for(int j=0;j<_blocks_in_set;j++)
                        {
                                int index=i*_blocks_in_set+j;
                                _valid_array[index]='i';
                                _dirty_array[index]='c';
                                _miss_or_hit_array[index]=0;
                        }
                }

                if(_use_stream_buffer==1)
                {
                        _tag_array_in_stream_buffer=new unsigned int[_p];
                        _valid_array_in_stream_buffer=new char[_p];
                }
        }

        void show_cache(FILE *f);
        void print_this_index(int this_index,int location);

        int simulate(char rw,unsigned int address,unsigned int global_time);
        void report(FILE *f);

        int bytes_in_block() {return _bytes_in_block;}

        /*
        int total_penalty()
        {
                return 12*(_reads_in_miss+_writes_in_miss);
        }
        */

        int total_num_of_miss()
        {
                return _reads_in_miss+_writes_in_miss;
        }

private:
        int _c; // 2^c bytes
        int _b; // 2^b byte blocks
        int _s; // 2^s blocks per set. 
                // Ex: s=0 direct-mapped cache
                //     s=c-b fully associative cache
        int _p; // prefetching sequentail blocks
        int _wp;        // wp=0 write back policy
                        // wp=1 write-through-no-allocate
        int _use_stream_buffer; // 0 use
                                // 1 no use

        int _bytes_in_cache;    // number of bytes in the cache
        int _sets_in_cache;     // number of sets in the cache
        int _blocks_in_set;     // number of blocks in one set
        int _bytes_in_block;    // number_of_bytes in one block

        unsigned int *_tag_array;       // store tags in cache
        unsigned int *_time_array;              // store time in cache
        int *_miss_or_hit_array;                // store hit or miss last time
        char *_valid_array;     // store valid bits v=>valid i=>invalid 
        char *_dirty_array;     // store direty bits, d=>dirty c=>clean

        unsigned int *_tag_array_in_stream_buffer;      // store tags in stream buffer
        char *_valid_array_in_stream_buffer;    // store valid bits in stream buffer

        int _reads;     // num of reads
        int _writes;    // num of writes
        int _reads_in_miss;     // num of read miss
        int _writes_in_miss;    // num of write miss
        int _writebacks;        // num of write backs from L1

        int _sb_reads_in_miss;
        int _sb_writes_in_miss;
};

//
// To support compress encoding in the memory
// Read: Instruction fetch mechanisms for VLIW architectures with compressed 
//       encoding
//
class Banked_Cache
{
    private:
    //HZ: The statistic of the banked cache.
    // Due to the characteristics of the banked cache, the total miss is not
    // equal to the misses of the two subbanks.
    // The reason: if a MOP requires two banks access (e.g., its start_address
    // is in bank 0 and end_address is in bank1) and both banks report miss,    
    // there would be two misses if we sum them up. However, as the miss can be
    // processed with a fetch of 2 consecutive blocks, this is only one miss
    // penalty actually.
    //So we keep account of the cache misses at this banked cache level
    int t_cache_access;
    int t_cache_misses;
    int t_cache_access_both_banks;
    
public:
        Banked_Cache():_bank0(NULL),_bank1(NULL),_block_size(0)
        {
                //_bank0=new Cache(14,5,0,0,0,0);       // 16K bytes, 32-byte line direct mapped
                //_bank1=new Cache(14,5,0,0,0,0);       // 16K bytes, 32-byte line direct mapped
        }

        Banked_Cache(int c,int b,int s):_c(c),_b(b),_s(s)
        {
                int half_size=_c-1;
                _block_size=1<<_b;

                //HZ: why??
                //It seems more associativity is a GOOD thing for miss rate.
                //assert(_s==0);        // ONLY WORK FOR DIRECT MAP NOW

                _bank0=new Cache(half_size,_b,_s,0,0,0);        
                _bank1=new Cache(half_size,_b,_s,0,0,0);
                
                //HZ:
                t_cache_access = 0;
                t_cache_misses = 0;
                t_cache_access_both_banks = 0;
        }

        ~Banked_Cache() 
        {
                delete _bank0;
                delete _bank1;
        }

        void simulate(char rw,unsigned int start_address,unsigned int num_of_op,unsigned int global_time)
        {
            //HZ:
            t_cache_access++;
                //
                // Step 1. calculate the end address of the last op
                //
                unsigned int end_address=start_address+(num_of_op-1)*4;
                unsigned int end_upper_portion=end_address>>_b;

                //
                // Step 2. Determine which banks to go
                //
                unsigned int start_upper_portion=start_address>>_b;
                unsigned int bank_id=start_upper_portion%2;

                //
                // Step 3. Check if we need to access two banks
                //
                bool need_only_one_bank=false;
                if(start_upper_portion==end_upper_portion)
                {
                        need_only_one_bank=true;
                }

                //
                // In order to reuse Cache class
                // Hack address for bank0 and bank1
                // => shift right 1 bit
                //
                unsigned int address_bank0=0;
                unsigned int address_bank1=0;

                if(bank_id==0)  // Fetch start from bank 0
                {
                        address_bank0=start_address>>1;

                        if(need_only_one_bank==true)
                        {
                            //HZ:
                            int hit_miss;
                            hit_miss = _bank0->simulate(rw,address_bank0,global_time);
                            assert(hit_miss <= 1);
                            t_cache_misses += (1 - hit_miss);
                                //_bank0->simulate(rw,address_bank0,global_time);
                        }
                        else    // access two banks
                        {
                            //HZ:
                            t_cache_access_both_banks++;
                                // bank1 use the same address
                                address_bank1=end_address>>1;

                                //HZ:
                                //_bank0->simulate(rw,address_bank0,global_time);
                                //_bank1->simulate(rw,address_bank1,global_time);
                                int hit_miss0, hit_miss1;
                                hit_miss0 = _bank0->simulate(rw,address_bank0,global_time);
                                assert(hit_miss0 <= 1);
                                hit_miss1 = _bank1->simulate(rw,address_bank1,global_time);
                                assert(hit_miss1 <= 1);
                                t_cache_misses += (1 - (hit_miss1 & hit_miss0)); 
                        }

                }
                else    // Fetch start from bank 1
                {
                        address_bank1=start_address>>1;

                        if(need_only_one_bank==true)
                        {
                            //HZ:
                            int hit_miss;
                            hit_miss = _bank1->simulate(rw,address_bank1,global_time);
                            assert(hit_miss <= 1);
                            t_cache_misses += (1 - hit_miss);
                                //_bank1->simulate(rw,address_bank1,global_time);
                        }
                        else    // access two banks
                        {
                            //HZ:
                            t_cache_access_both_banks++;
                                // bank0 use the different address
                                address_bank0=end_address>>1;

                                //HZ:
                                //_bank1->simulate(rw,address_bank1,global_time);
                                //_bank0->simulate(rw,address_bank0,global_time);
                                int hit_miss0, hit_miss1;
                                hit_miss1 = _bank1->simulate(rw,address_bank1,global_time);
                                assert(hit_miss1 <= 1);
                                hit_miss0 = _bank0->simulate(rw,address_bank0,global_time);
                                assert(hit_miss0 <= 1);
                                t_cache_misses += (1 - (hit_miss1 & hit_miss0));                                
                        }
                }

                //fprintf(stderr,"Start Address is %u\n",start_address);
                //fprintf(stderr,"End Address is %u\n",end_address);
                //fprintf(stderr,"Fetch one bank=%d\nFrom bank %d: bank0 %u bank1 %u\n",need_only_one_bank,bank_id,address_bank0,address_bank1);

        }

        void show_cache(FILE *f);
        void report(FILE *f);
        //int total_penalty();

        int total_num_of_miss();

private:
        Cache *_bank0;
        Cache *_bank1;

        int _c; // 2^c bytes
        int _b; // 2^b byte blocks
        int _s; // 2^s blocks per set. 
                // Ex: s=0 direct-mapped cache
                //     s=c-b fully associative cache
        unsigned int _block_size;       // size of block = 2^_b
};

#endif // INCLUDED_CACHE_H

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