Eric Rotenberg's Website -- Publications

Conference and Journal Papers

2008

V. K. Reddy and E. Rotenberg. Coverage of a Microarchitecture-level Fault Check Regimen in a Superscalar Processor. Proceedings of the 38th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-38, DCCS track), pp. ??-??, June 2008. [pdf]

H. Hashemi Najaf-abadi and E. Rotenberg. Configurational Workload Characterization. Proceedings of the 2008 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'08), pp. 147-156, April 2008. [pdf]

2007

V. K. Reddy and E. Rotenberg. Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. Proceedings of the 37th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-37, DCCS track), pp. 307-316, June 2007. [pdf]

A. S. Al-Zawawi, V. K. Reddy, E. Rotenberg, and H. Akkary. Transparent Control Independence (TCI). Proceedings of the 34th IEEE/ACM International Symposium on Computer Architecture (ISCA-34), pp. 448-459, June 2007. [pdf]

R. K. Venkatesan, A. S. AL-Zawawi, K. Siva, and E. Rotenberg. ZettaRAM^TM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling. IEEE Transactions on Computers, Special Section on Nano Systems and Computing, 56(2):147-160, February 2007. [pdf]

2006

V. K. Reddy, S. Parthasarathy, and E. Rotenberg. Understanding Prediction-Based Partial Redundant Threading for Low-Overhead, High-Coverage Fault Tolerance. Proceedings of the 12th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), pp. 83-94, October 2006. [pdf]

V. K. Reddy, A. S. Al-Zawawi, and E. Rotenberg. Assertion-Based Microarchitecture Design for Improved Fault Tolerance. Proceedings of the 24th IEEE International Conference on Computer Design (ICCD-24), pp. 362-369, October 2006. [pdf]

E. Rotenberg and R. K. Venkatesan. The State of ZettaRAM. Proceedings of the 1st IEEE International Conference on Nano-Networks, pp. 1-5, September 2006. [pdf]

R. K. Venkatesan, S. Herr, and E. Rotenberg. Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM. Proceedings of the 12th IEEE International Symposium on High-Performance Computer Architecture (HPCA-12), pp. 157-167, February 2006. [pdf]

K. Seth, A. Anantaraman, F. Mueller, and E. Rotenberg. FAST: Frequency-Aware Static Timing Analysis. ACM Transactions on Embedded Computing Systems (TECS), 5(1):200-224, February 2006.

A. Anantaraman and E. Rotenberg. Non-Uniform Program Analysis & Repeatable Execution Constraints: Exploiting Out-of-Order Processors in Real-Time Systems. ACM SIGBED Review, Volume 3, Number 1, January 2006. [pdf]

2005

A. El-Haj-Mahmoud, A. S. AL-Zawawi, A. Anantaraman, and E. Rotenberg. Virtual Multiprocessor: An Analyzable, High-Performance Microarchitecture for Real-Time Computing. Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'05), pp. 213-224, September 2005. [pdf]

R. K. Venkatesan, A. S. AL-Zawawi, and E. Rotenberg. Tapping ZettaRAM^TM for Low-Power Memory Systems. Proceedings of the 11th IEEE International Symposium on High-Performance Computer Architecture (HPCA-11), pp. 83-94, February 2005. [pdf]

2004

A. Anantaraman, K. Seth, E. Rotenberg, and F. Mueller. Enforcing Safety of Real-Time Schedules on Contemporary Processors Using a Virtual Simple Architecture (VISA). Proceedings of the 25th IEEE International Real-Time Systems Symposium (RTSS-25), pp. 114-125, December 2004. [pdf]

A. El-Haj-Mahmoud and E. Rotenberg. Safely Exploiting Multithreaded Processors to Tolerate Memory Latency in Real-Time Systems. Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'04), pp. 2-13, September 2004. [pdf]

J. J. Koppanalil and E. Rotenberg. A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. IEEE Transactions on Computers, 53(4):399-413, April 2004.

2003

K. Seth, A. Anantaraman, F. Mueller, and E. Rotenberg. FAST: Frequency-Aware Static Timing Analysis. Proceedings of the 24th IEEE International Real-Time Systems Symposium (RTSS-24), pp. 40-51, December 2003.

H. Zhou, M. C. Toburen, E. Rotenberg, and T. M. Conte. Adaptive Mode Control: A Static-Power-Efficient Cache Design. ACM Transactions on Embedded Computing Systems (TECS), Special issue on power-aware embedded computing, 2(3):347-372, August 2003.

A. Anantaraman, K. Seth, K. Patil, E. Rotenberg, and F. Mueller. Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems. Proceedings of the 30th IEEE/ACM International Symposium on Computer Architecture (ISCA-30), pp. 350-361, June 2003. [pdf]

K. Z. Ibrahim, G. T. Byrd, and E. Rotenberg. Slipstream Execution Mode for CMP-Based Multiprocessors. Proceedings of the 9th IEEE International Symposium on High-Performance Computer Architecture (HPCA-9), pp. 179-190, February 2003. [pdf]

2002

J. Koppanalil, P. Ramrakhyani, S. Desai, A. Vaidyanathan, and E. Rotenberg. A Case for Dynamic Pipeline Scaling. Proceedings of the 5th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'02), pp. 1-8, October 2002. [pdf]

A. R. Lebeck, J. J. Koppanalil, T. Li, J. Patwardhan, and E. Rotenberg. A Large, Fast Instruction Window for Tolerating Cache Misses. Proceedings of the 29th IEEE/ACM International Symposium on Computer Architecture (ISCA-29), pp. 59-70, May 2002. [pdf]

2001

E. Rotenberg. Using Variable-MHz Microprocessors to Efficiently Handle Uncertainty in Real-Time Systems. Proceedings of the 34th IEEE/ACM International Symposium on Microarchitecture (MICRO-34), pp. 28-39, December 2001. [pdf]

H. Zhou, M. C. Toburen, E. Rotenberg, and T. M. Conte. Adaptive Mode Control: A Static-Power-Efficient Cache Design. Proceedings of the 10th IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT'01), pp. 61-70, September 2001. [pdf]

2000

Z. Purser, K. Sundaramoorthy, and E. Rotenberg. A Study of Slipstream Processors. Proceedings of the 33rd IEEE/ACM International Symposium on Microarchitecture (MICRO-33), pp. 269-280, December 2000. [pdf]

K. Sundaramoorthy, Z. Purser, and E. Rotenberg. Slipstream Processors: Improving both Performance and Fault Tolerance. Proceedings of the 9th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-9), pp. 257-268, November 2000. [pdf]

Eric Rotenberg and James E. Smith. Control Independence in Trace Processors. Journal of Instruction-Level Parallelism (JILP), Special issue - papers from MICRO-32, vol. 2, pp. 63-85, May 2000. [pdf]

1999

Eric Rotenberg and James E. Smith. Control Independence in Trace Processors. Proceedings of the 32nd IEEE/ACM International Symposium on Microarchitecture (MICRO-32), pp. 4-15, November 1999. [pdf]

Eric Rotenberg. AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. Proceedings of the 29th IEEE International Symposium on Fault-Tolerant Computing (FTCS-29), pp. 84-91, June 1999. [pdf]

Eric Rotenberg, Steve Bennett, and James E. Smith. A Trace Cache Microarchitecture and Evaluation. IEEE Transactions on Computers, Special Issue on Cache Memory, 48(2):111-120, February 1999. [pdf]

Eric Rotenberg, Quinn Jacobson, and James E. Smith. A Study of Control Independence in Superscalar Processors. Proceedings of the 5th IEEE International Symposium on High-Performance Computer Architecture (HPCA-5), pp. 115-124, January 1999. [pdf]
Also see detailed Technical Report.

1997

Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, and James E. Smith. Trace Processors. Proceedings of the 30th IEEE/ACM International Symposium on Microarchitecture (MICRO-30), pp. 138-148, December 1997. [pdf]

Quinn Jacobson, Eric Rotenberg, and James E. Smith. Path-Based Next Trace Prediction. Proceedings of the 30th IEEE/ACM International Symposium on Microarchitecture (MICRO-30), pp. 14-23, December 1997. [pdf]

1996

Erik Jacobsen, Eric Rotenberg, and James E. Smith. Assigning Confidence to Conditional Branch Predictions. Proceedings of the 29th IEEE/ACM International Symposium on Microarchitecture (MICRO-29), pp. 142-152, December 1996. [pdf]

Eric Rotenberg, Steve Bennett, and James E. Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. Proceedings of the 29th IEEE/ACM International Symposium on Microarchitecture (MICRO-29), pp. 24-34, December 1996. [pdf]
Also see detailed Technical Report.

Workshop Papers

H. H. Najaf-abadi and E. Rotenberg. Exploiting Detachability: A Non-Silicon Approach to Polymorphism. Proceedings of the 4th Workshop on Non-Silicon Computing (NSC-4), in conjunction with ISCA-34, June 2007.

H. H. Najaf-abadi and E. Rotenberg. Architectural Contesting: Exposing and Exploiting Temperamental Behavior.

Proceedings of the Reconfigurable and Adaptive Architecture Workshop (RAAW), in conjunction with MICRO-39, December 2006.
Also appears in ACM SIGARCH Computer Architecture News (CAN), 35(3):28-35, June 2007. [pdf ]

A. Anantaraman and E. Rotenberg. Non-Uniform Program Analysis & Repeatable Execution Constraints: Exploiting Out-of-Order Processors in Real-Time Systems. Work in Progress Session for the 26th IEEE International Real-Time Systems Symposium (RTSS-26), December 2005. [pdf]

Technical Reports

A. Anantaraman, K. Seth, E. Rotenberg, and F. Mueller. Exploiting VISA for Higher Concurrency in Safe Real-Time Systems. Technical Report TR-2004-15, Department of Computer Science, North Carolina State University, May 2004. [pdf]

Z. Purser, K. Sundaramoorthy, and E. Rotenberg. Slipstream Memory Hierarchies. Technical Report CESR-TR-02-3, Center for Embedded Systems Research, Department of Electrical and Computer Engineering, North Carolina State University, February 2002. [pdf]

K. Sundaramoorthy, Z. Purser, and E. Rotenberg. Multipath Execution on Chip Multiprocessors Enabled by Redundant Threads. Technical Report CESR-TR-01-2, Center for Embedded Systems Research, Department of Electrical and Computer Engineering, North Carolina State University, October 2001. [pdf]

Ashwini Sidhaye, Paul Steinmetz, Eric Rotenberg, David Barrow, and Domenico Arpaia. Collecting Memory Address Traces from an Ericsson Cell Phone and Estimating Cache Performance. Technical Report CESR-TR-01-1, Center for Embedded Systems Research, Department of Electrical and Computer Engineering, North Carolina State University, August 2001. [pdf]

Eric Rotenberg. Exploiting Large Ineffectual Instruction Sequences. Technical Report, North Carolina State University, November 1999. [pdf]

Eric Rotenberg, Quinn Jacobson, and James E. Smith. A Study of Control Independence in Superscalar Processors. University of Wisconsin - Madison Technical Report #1389, December 1998. [pdf]

Eric Rotenberg, Steve Bennett, and James E. Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. University of Wisconsin - Madison Technical Report #1310, April 1996. [pdf]

Book Chapters

E. Rotenberg. Trace Caches, in Speculative Execution in High Performance Computer Architectures. D. Kaeli and P.-C. Yew, Eds. CRC Press, 2005.

E. Rotenberg and A. Anantaraman. Architecture of Embedded Microprocessors, in Multiprocessor Systems-on-Chips. Ahmed Jerraya and Wayne Wolf, Eds. San Francisco, CA: Morgan Kaufmann Publishers, 2005, pp. 81-112.

E. Rotenberg. Trace Caching and Trace Processors, in The Computer Engineering Handbook. Vojin Oklobdzija, Ed. CRC Press, 2001, pp. 8-37 -- 8-45.

Theses

Eric Rotenberg. Trace Processors: Exploiting Hierarchy and Speculation. Ph.D. Thesis, University of Wisconsin - Madison, August 1999. [pdf]

Student Theses

V. K. Reddy. Exploiting Microarchitecture Insights for Efficient Fault Tolerance. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, August 2007. [NCSU library: on-line thesis]

A. S. Al-Zawawi. Transparent Control Independence (TCI). Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, August 2007. [NCSU library: on-line thesis]

R. K. Venkatesan. Power-Scalable Memory: Exploiting Typical Charge Retention in DRAM and Charge-Voltage Decoupling in ZettaRAM. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, July 2006. [NCSU library: on-line thesis]

M. M. Al-Otoom. Preliminary Study of Trace-Cache-Based Control Independence Architecture. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2006. [NCSU library: on-line thesis]

A. A. El-Haj-Mahmoud. Hard-Real-Time Multithreading: A Combined Microarchitectural and Scheduling Approach. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2006. [NCSU library: on-line thesis]

A. V. Anantaraman. Analysis-Managed Processor (AMP): Exceeding the Complexity Limit in Safe-Real-Time Systems. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, April 2006. [NCSU library: on-line thesis]

S. Parthasarathy. Improving Transient Fault Tolerance of Slipstream Processors. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, December 2005. [NCSU library: on-line thesis]

Z. R. Purser. Slipstream Processors. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, July 2003. [NCSU library: on-line dissertation]

N. Gupta. Slipstream-Based Steering for Clustered Microarchitectures. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2003. [pdf]

P. S. Ramrakhyani. Dynamic Pipeline Scaling. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2003. [pdf]

A. V. Anantaraman. Reducing Frequency in Real-Time Systems via Speculation and Fall-Back Recovery. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, April 2003. [pdf]

J. J. Koppanalil. A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2002. [pdf]

Patents

E. Rotenberg, R. K. Venkatesan, and A. S. AL-Zawawi. Systems, Methods and Devices for Providing Variable-Latency Write Operations in Memory Devices. US Patent #7,099,215. Filed Feb. 11, 2005. Issued Aug. 29, 2006.

E. Rotenberg and J. Lindsey. Variable-Persistence Molecular Memory Devices and Methods of Operation Thereof. US Patent #6,944,047. Filed Dec. 19, 2002. Issued Sep. 13, 2005.

My Course Projects from UW-Madison

Mark D. Callaghan, Mohammed M. Hoque, and Eric Rotenberg. Level-Two Translation Lookaside Buffers. CS 752: Advanced Computer Architecture I (Prof. M. Hill), Fall Semester 1994. [ps]

Emmanuel Ackaouy and Eric Rotenberg. A Comparison of SCI and Typhoon. CS 757: Advanced Computer Architecture II (Prof. J. Goodman), Spring Semester 1995. [ps]

Eric Rotenberg. An Analytical Model of the SCI Coherence Protocol. CS 747: Advanced Computer System Performance Modeling (Prof. M. Vernon), Spring Semester 1995. [ps]

Quinn Jacobson and Eric Rotenberg. Custom VLSI Design of a Programmable Digital Filter. ECE 755: VLSI Systems Design (Prof. P. Ramanathan), Fall Semester 1995. [ps]

Quinn Jacobson and Eric Rotenberg. Local Instruction Scheduling. CS 701: Programming Languages and Compilers (Prof. C. Fischer), Spring Semester 1996. [ps]

Eric Rotenberg, Paul Thayer, and Jeremy Williamson. Full Shared Memory Support in Blizzard-S. CS 736: Advanced Operating Systems (Prof. Pei Cao), Spring Semester 1996.

Eric Rotenberg. AR-SMT: Coarse-Grain Time Redundancy for High Performance General Purpose Computers. ECE 753: Fault-Tolerant Computing (Prof. K. Saluja), Spring Semester 1998.

Course project paper (May 14, 1998). [ps]
Course project talk (May 10, 1998). [ps] Can you find the error in the figure of slide 13?
This project led to a FTCS-29 conference paper.