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Research Projects
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This project investigates new ways to exploit chip multiprocessors (CMP) and simultaneous multithreading processors (SMT),
and expand their capabilities. The ability to execute multiple tasks at the same time within a single microprocessor chip
opens up major opportunities for increasing the performance, functionality, and reliability of computers.
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There is growing concern that transient faults, caused by cosmic rays and other factors,
will occur frequently in future high-performance processors, as designers push technology to its
extreme limits. Existing fault-tolerant techniques are either too costly (system-level replication),
too intrusive (gate-level replication), or too specific (e.g., ECC on memory). In 1999,
we proposed a microarchitectural approach to fault tolerance (AR-SMT), achieving broad coverage of transient
faults with low performance overhead and few changes to the underlying microarchitecture.
We revisit this notion and explore other ways the microarchitecture can help reliability.
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In the area of high-performance processors, there remain only a few
dogged bottlenecks that fundamentally constrain performance, i.e., these
bottlenecks render additional millions of transistors mostly ineffective.
This project attacks one of the remaining grand-challenge problems in scaling microprocessor
performance: ambiguous control-flow.
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Due to increasing functionality in cell phones, cameras, cars, and other embedded systems,
high-end embedded processors are inheriting high-performance techniques from their desktop counterparts,
such as pipelining, caches, dynamic branch prediction, and multithreading. Unfortunately, while these
techniques perform well on average, their performance cannot be analytically bounded, a key safety requirement
for embedded systems with real-time tasks. In this project, we are pioneering new directions for designing
higher performance real-time embedded systems without compromising safety.
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The importance of mass storage cannot be overstated. Most users really care about their files and information.
Computer architectures are heavily influenced by parameters imposed by memory technologies.
We are interested in all parameters of mass storage
(volatility, speed, power, density, cost, reliability) and intrigued by the diversity of
prevailing and nascent memory technologies.
In the near term, since mass storage is increasingly important in portable devices,
we are investigating ways of achieving very low-power memory, exploiting both
conventional technologies (e.g., DRAM) and more exotic ones.
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A new microarchitecture project
Coming soon... This new microarchitecture project is sponsored by Intel, NSF, and SRC.
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